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"Hardware Description Language Enhancements for High Level Synthesis of ..."

Gurusankar Kasivinayagam et al. (2022)

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DOI: 10.1007/978-3-031-12638-3_1

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-05

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Gurusankar Kasivinayagam, Romaanchan Skanda, Aditya G. Burli, Shruti Jadon, Reetinder Sidhu:
Hardware Description Language Enhancements for High Level Synthesis of Hardware Accelerators. ICACDS (1) 2022: 1-12

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