"Design of a high speed, low power synchronously clocked NOR-based JK ..."

Krishnendu Dhar (2014)

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DOI: 10.1109/ICACCI.2014.6968212

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Krishnendu Dhar:
Design of a high speed, low power synchronously clocked NOR-based JK flip-flop using modified GDI technique in 45nm technology. ICACCI 2014: 600-606

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