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"Power-Efficient Secured Hardware Design of AES Algorithm on High ..."

Keshav Kumar et al. (2022)

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DOI: 10.1109/IC3I56241.2022.10073148

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

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Keshav Kumar, Vijay Singh, Gaurav Mishra, Bellam Ravindra Babu, Nandita Tripathi, Pramod Kumar:
Power-Efficient Secured Hardware Design of AES Algorithm on High Performance FPGA. IC3I 2022: 1634-1637

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