"A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCO."

Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski (2005)

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DOI: —

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type: Conference or Workshop Paper

metadata version: 2007-07-23

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  dblp key:
  - conf/iastedCCS/ZhuangDK05
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  - https://dblp.org/rec/conf/iastedCCS/ZhuangDK05
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski:
A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCO. Circuits, Signals, and Systems 2005: 128-131

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