BibTeX record conf/hpca/IyengarTB96

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@inproceedings{DBLP:conf/hpca/IyengarTB96,
  author    = {Vijay S. Iyengar and
               Louise Trevillyan and
               Pradip Bose},
  title     = {Representative Traces for Processor Models with Infinite Cache},
  booktitle = {Proceedings of the Second International Symposium on High-Performance
               Computer Architecture, San Jose, CA, USA, February 3-7, 1996},
  pages     = {62--72},
  year      = {1996},
  crossref  = {DBLP:conf/hpca/1996},
  url       = {https://doi.org/10.1109/HPCA.1996.501174},
  doi       = {10.1109/HPCA.1996.501174},
  timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl    = {https://dblp.org/rec/conf/hpca/IyengarTB96.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hpca/1996,
  title     = {Proceedings of the Second International Symposium on High-Performance
               Computer Architecture, San Jose, CA, USA, February 3-7, 1996},
  publisher = {{IEEE} Computer Society},
  year      = {1996},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/3595/proceeding},
  isbn      = {0-8186-7237-4},
  timestamp = {Thu, 19 May 2022 21:09:18 +0200},
  biburl    = {https://dblp.org/rec/conf/hpca/1996.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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