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"Gate matrix layout based on hierarchical net-list representations."

Shigeki Yamada, Kazuhiro Yamazaki (1991)

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DOI: 10.1109/GLSV.1991.143981

access: closed

type: Conference or Workshop Paper

metadata version: 2019-12-17

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Shigeki Yamada, Kazuhiro Yamazaki:
Gate matrix layout based on hierarchical net-list representations. Great Lakes Symposium on VLSI 1991: 290-295

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