"Parallel pipelined FFT architectures with reduced number of delays."

Manohar Ayinala, Keshab K. Parhi (2012)

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DOI: 10.1145/2206781.2206798

access: closed

type: Conference or Workshop Paper

metadata version: 2024-08-04

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Manohar Ayinala, Keshab K. Parhi:
Parallel pipelined FFT architectures with reduced number of delays. ACM Great Lakes Symposium on VLSI 2012: 63-66

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