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"Low-power clock distribution in a multilayer core 3d microprocessor."

Venkatesh Arunachalam, Wayne P. Burleson (2008)

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DOI: 10.1145/1366110.1366212

access: closed

type: Conference or Workshop Paper

metadata version: 2020-04-06

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  dblp key:
  - conf/glvlsi/ArunachalamB08
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  - https://dblp.org/rec/conf/glvlsi/ArunachalamB08
Venkatesh Arunachalam, Wayne P. Burleson:
Low-power clock distribution in a multilayer core 3d microprocessor. ACM Great Lakes Symposium on VLSI 2008: 429-434

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