"Systolic Array-Based Accelerator Architecture Combining Iterative ..."

Po-Ying Feng et al. (2024)

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DOI: 10.1109/GCCE62371.2024.10760601

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type: Conference or Workshop Paper

metadata version: 2024-12-12

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Po-Ying Feng, Shih-Nung Lee, Yong-Chi Chang, Hsuan-Yu Chiang, Shu-Yen Lin:
Systolic Array-Based Accelerator Architecture Combining Iterative Variable-Width Approximate Multipliers. GCCE 2024: 98-99

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