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"Improving Security of SDDL Designs through Interleaved Placement on Xilinx ..."

Rajesh Velegalati, Jens-Peter Kaps (2011)

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DOI: 10.1109/FPL.2011.100

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Rajesh Velegalati, Jens-Peter Kaps:
Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs. FPL 2011: 506-511

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