"Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor ..."

Edoardo Fusella, Alessandro Cilardo, Antonino Mazzeo (2015)

Details and statistics

DOI: 10.1109/FPL.2015.7293989

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

a service of  Schloss Dagstuhl - Leibniz Center for Informatics