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"Variable-latency signed addition on FPGAs."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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Alessandro Cilardo (2015)

Trier

Dagstuhl

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DOI: 10.1109/FPL.2015.7293957

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Alessandro Cilardo:
Variable-latency signed addition on FPGAs. FPL 2015: 1-6

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last updated on 2017-05-21 00:20 CEST by the dblp team

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