"SSR: Spatial Sequential Hybrid Architecture for Latency Throughput ..."

Jinming Zhuang et al. (2024)

> Home

Details and statistics

DOI: 10.1145/3626202.3637569

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpga/ZhuangYJHJH0024
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpga/ZhuangYJHJH0024
Jinming Zhuang, Zhuoping Yang, Shixin Ji, Heng Huang, Alex K. Jones, Jingtong Hu, Yiyu Shi, Peipei Zhou:
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration. FPGA 2024: 55-66

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.