"Low-Latency, Line-Rate Variable-Length Field Parsing for 100+ Gb/s Ethernet."

Greg Stitt, Wesley Piard, Christopher Crary (2024)

> Home

Details and statistics

DOI: 10.1145/3626202.3637559

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpga/StittPC24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpga/StittPC24
Greg Stitt, Wesley Piard, Christopher Crary:
Low-Latency, Line-Rate Variable-Length Field Parsing for 100+ Gb/s Ethernet. FPGA 2024: 12-21

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.