Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Automatic generation of high-performance multipliers for FPGAs with ..."

Shreesha Srinath, Katherine Compton (2010)

> Home

Details and statistics

DOI: 10.1145/1723112.1723123

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpga/SrinathC10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpga/SrinathC10
Shreesha Srinath, Katherine Compton:
Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks. FPGA 2010: 51-58

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.