"Speedy: An Accelerator for Sparse Convolutional Neural Networks on FPGAs."

Liqiang Lu et al. (2019)

> Home

Details and statistics

DOI: 10.1145/3289602.3293970

access: closed

type: Conference or Workshop Paper

metadata version: 2025-05-16

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpga/Lu0HLCZ19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpga/Lu0HLCZ19
Liqiang Lu, Yun Liang, Ruirui Huang, Wei Lin, Xiaoyuan Cui, Jiansong Zhang:
Speedy: An Accelerator for Sparse Convolutional Neural Networks on FPGAs. FPGA 2019: 187

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.