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"A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS ..."

Mingqiang Huang et al. (2022)

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DOI: 10.1145/3490422.3502343

access: closed

type: Conference or Workshop Paper

metadata version: 2022-03-13

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  dblp key:
  - conf/fpga/HuangLCYLLYLYM22
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  - https://dblp.org/rec/conf/fpga/HuangLCYLLYLYM22
Mingqiang Huang, Yucen Liu, Quan Cheng, Shuxin Yang, Kai Li, Junyi Luo, Zhengke Yang, Qiufeng Li, Hao Yu, Changhai Man:
A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA. FPGA 2022: 50

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