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"The effect of post-layout pin permutation on timing."

Yuzheng Ding, Peter Suaris, Nan-Chi Chou (2005)

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DOI: 10.1145/1046192.1046199

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/fpga/DingSC05
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  - https://dblp.org/rec/conf/fpga/DingSC05
Yuzheng Ding, Peter Suaris, Nan-Chi Chou:
The effect of post-layout pin permutation on timing. FPGA 2005: 41-50

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