"Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by ..."

Miroslav N. Velev, Randal E. Bryant (1998)

> Home

Details and statistics

DOI: 10.1007/3-540-49519-3_3

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fmcad/VelevB98
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fmcad/VelevB98
Miroslav N. Velev, Randal E. Bryant:
Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking. FMCAD 1998: 18-35

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.