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"Flexible runtime verification based on logical clock constraints."

Daian Yue, Vania Joloboff, Frédéric Mallet (2016)

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DOI: 10.1109/FDL.2016.7880366

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-15

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  dblp key:
  - conf/fdl/YueJM16
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  - https://dblp.org/rec/conf/fdl/YueJM16
Daian Yue, Vania Joloboff, Frédéric Mallet:
Flexible runtime verification based on logical clock constraints. FDL 2016: 1-8

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