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"PIR-DSP: An FPGA DSP Block Architecture for Multi-precision Deep Neural ..."

Seyedramin Rasoulinezhad et al. (2019)

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DOI: 10.1109/FCCM.2019.00015

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-02

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Seyedramin Rasoulinezhad, Hao Zhou, Lingli Wang, Philip H. W. Leong:
PIR-DSP: An FPGA DSP Block Architecture for Multi-precision Deep Neural Networks. FCCM 2019: 35-44

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