"Exploiting the Use of VHDL Specifications in the AGENDA High-Level ..."

George Economakos, George K. Papakonstantinou (1998)

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DOI: 10.1109/EURMIC.1998.711782

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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George Economakos, George K. Papakonstantinou:
Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis Environment. EUROMICRO 1998: 10091-10098

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