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"A novel test time reduction algorithm for test architecture design for ..."

Sandeep Kumar Goel, Erik Jan Marinissen (2002)

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DOI: 10.1109/ETW.2002.1029633

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-05

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Sandeep Kumar Goel, Erik Jan Marinissen:
A novel test time reduction algorithm for test architecture design for core-based system chips. ETW 2002: 7-12

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