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"SPICE modeling in Verilog-A: Successes and challenges: Invited paper."

Colin C. McAndrew (2017)

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DOI: 10.1109/ESSDERC.2017.8066582

access: closed

type: Conference or Workshop Paper

metadata version: 2017-10-19

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  dblp key:
  - conf/essderc/McAndrew17
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  - https://dblp.org/rec/conf/essderc/McAndrew17
Colin C. McAndrew:
SPICE modeling in Verilog-A: Successes and challenges: Invited paper. ESSDERC 2017: 22-25

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