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"A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS ..."

Paul Madeira, Marc-Andre LaCroix, John Hogeboom (2007)

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DOI: 10.1109/ESSCIRC.2007.4430359

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-18

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  dblp key:
  - conf/esscirc/MadeiraLH07
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Paul Madeira, Marc-Andre LaCroix, John Hogeboom:
A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS technology. ESSCIRC 2007: 532-535

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