"Design of A Bit-Serial Artificial Neuron VLSI Architecture with Early ..."

Yun-Nan Chang, Guan-Jhen Chen (2019)

> Home

Details and statistics

DOI: 10.23919/ELINFOCOM.2019.8706444

access: closed

type: Conference or Workshop Paper

metadata version: 2019-12-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/elinfocom/ChangC19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/elinfocom/ChangC19
Yun-Nan Chang, Guan-Jhen Chen:
Design of A Bit-Serial Artificial Neuron VLSI Architecture with Early Termination. ICEIC 2019: 1-3

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.