"Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA ..."

Francesco Restuccia et al. (2020)

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DOI: 10.4230/LIPICS.ECRTS.2020.12

access: open

type: Conference or Workshop Paper

metadata version: 2024-05-07

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Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, Giorgio C. Buttazzo:
Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs. ECRTS 2020: 12:1-12:23

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