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"Design of a SystemVerilog-Based Sigma-Delta ADC Real Number Model."

Constantina Tsechelidou, Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos (2019)

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DOI: 10.1109/DSD.2019.00028

access: closed

type: Conference or Workshop Paper

metadata version: 2020-10-25

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  dblp key:
  - conf/dsd/TsechelidouGH19
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  - https://dblp.org/rec/conf/dsd/TsechelidouGH19
Constantina Tsechelidou, Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos:
Design of a SystemVerilog-Based Sigma-Delta ADC Real Number Model. DSD 2019: 124-128

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