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"Scheduling voter checks to detect configuration memory errors in ..."

Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel (2017)

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DOI: 10.1109/DFT.2017.8244455

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/dft/NguyenCD17
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  - https://dblp.org/rec/conf/dft/NguyenCD17
Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel:
Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems. DFT 2017: 1-4

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