Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Hardware architecture for lowering the error floor of LTE turbo codes."

Thibaud Tonnellier et al. (2016)

> Home

Details and statistics

DOI: 10.1109/DASIP.2016.7853805

access: closed

type: Conference or Workshop Paper

metadata version: 2019-10-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/dasip/TonnellierLGJGW16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/dasip/TonnellierLGJGW16
Thibaud Tonnellier, Camille Leroux, Bertrand Le Gal, Christophe Jégo, Benjamin Gadat, Nicolas Van Wambeke:
Hardware architecture for lowering the error floor of LTE turbo codes. DASIP 2016: 107-112

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.