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"Time-Division Multiplexing Based System-Level FPGA Routing for Logic ..."

Peng Zou et al. (2020)

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DOI: 10.1109/DAC18072.2020.9218569

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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  dblp key:
  - conf/dac/ZouLSWCYC20
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  - https://dblp.org/rec/conf/dac/ZouLSWCYC20
Peng Zou, Zhifeng Lin, Xiao Shi, Yingjie Wu, Jianli Chen, Jun Yu, Yao-Wen Chang:
Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification. DAC 2020: 1-6

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