"Low power network processor design using clock gating."

Yan Luo et al. (2005)

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DOI: 10.1145/1065579.1065766

access: closed

type: Conference or Workshop Paper

metadata version: 2019-09-26

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Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan:
Low power network processor design using clock gating. DAC 2005: 712-715

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