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"A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle ..."
Vikas Singh et al. (2011)
- Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, Debasish Behera:
A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay. CICC 2011: 1-4
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