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"A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for ..."

Dirk Pfaff et al. (2019)

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DOI: 10.1109/CICC.2019.8780247

access: closed

type: Conference or Workshop Paper

metadata version: 2019-08-07

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Dirk Pfaff, Robert Abbott, Xin-Jie Wang, Babak Zamanlooy, Shahaboddin Moazzeni, Raleigh Smith, Chih-Chang Lin:
A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET. CICC 2019: 1-4

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