"A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock ..."

Tae-Young Oh et al. (2006)

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DOI: 10.1109/CICC.2006.320966

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Tae-Young Oh, Seung-Hyun Yi, Sung-Hyun Yang, Byong-Chan Lim, Kuk-Tae Hong:
A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery. CICC 2006: 745-748

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