"A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond."

Yoshihide Komatsu et al. (2004)

Details and statistics

DOI: 10.1109/CICC.2004.1358812

access: closed

type: Conference or Workshop Paper

metadata version: 2017-08-21

a service of  Schloss Dagstuhl - Leibniz Center for Informatics