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"A 28nm All-Digital Droop Detection and Mitigation Circuit Using a Shared ..."

Minyoung Kang et al. (2024)

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DOI: 10.1109/CICC60959.2024.10528973

access: closed

type: Conference or Workshop Paper

metadata version: 2024-06-03

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Minyoung Kang, Sunghoon Kim, Youngmin Park, Sangsu Jeong, Dongsuk Jeon:
A 28nm All-Digital Droop Detection and Mitigation Circuit Using a Shared Dual-Mode Delay Line with 14.8% VminReduction and 42.9% Throughput Gain. CICC 2024: 1-2

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