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"A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive ..."

Markus Hiienkari et al. (2014)

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DOI: 10.1109/CICC.2014.6946095

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Markus Hiienkari, Jukka Teittinen, Lauri Koskinen, Matthew J. Turnquist, Mikko Kaltiokallio:
A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS. CICC 2014: 1-4

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