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"12× bit-error acceptable, 300× extended data-retention time, ..."

Yoshiaki Deguchi et al. (2017)

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DOI: 10.1109/CICC.2017.7993687

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

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  - conf/cicc/DeguchiNKT17
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  - https://dblp.org/rec/conf/cicc/DeguchiNKT17
Yoshiaki Deguchi, Toshiki Nakamura, Atsuro Kobayashi, Ken Takeuchi:
12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition. CICC 2017: 1-4

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