"Security Improvement of FPGA Design Against Timing Side Channel Attack ..."

Pourya Bayat-Makou, Ali Jahanian, Midia Reshadi (2018)

> Home

Details and statistics

DOI: 10.1109/CCECE.2018.8447738

access: closed

type: Conference or Workshop Paper

metadata version: 2019-09-18

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ccece/Bayat-MakouJR18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ccece/Bayat-MakouJR18
Pourya Bayat-Makou, Ali Jahanian, Midia Reshadi:
Security Improvement of FPGA Design Against Timing Side Channel Attack Using Dynamic Delay Management. CCECE 2018: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.