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"An Ultra-low-power 28nm CMOS Dual-die ASIC Platform for Smart Hearables."
Yu Pu et al. (2018)
- Yu Pu, Danny Butterfield, Jorge Garcia, Jing Xie, Mark Lin, Rohit Sauhta, Rick Farley, Steve Shellhammer, Moses Derkalousdian, Adam Newham, Chunlei Shi, Ravi Shenoy, Evgeni Gousev, Rashid Attar:
An Ultra-low-power 28nm CMOS Dual-die ASIC Platform for Smart Hearables. BioCAS 2018: 1-4
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