"Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter."

Guan-Hao Hou et al. (2018)

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DOI: 10.1109/ATS.2018.00047

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Guan-Hao Hou, Wei-Chen Huang, Jiun-Lang Huang, Terry Kuo:
Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter. ATS 2018: 209-214

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