"Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan ..."

Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (2018)

> Home

Details and statistics

DOI: 10.1109/ATS.2018.00013

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/ats/HiraiYH18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ats/HiraiYH18
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design. ATS 2018: 7-12

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.