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"A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital ..."

Chun-Yuan Cheng et al. (2014)

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DOI: 10.1109/ASSCC.2014.7008935

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Chun-Yuan Cheng, Jinn-Shyan Wang, Pei-Yuan Chou, Shiou-Ching Chen, Chi-Tien Sun, Yuan-Hua Chu, Tzu-Yi Yang:
A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm² all-digital delay-locked loop in 65-nm CMOS. A-SSCC 2014: 361-364

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