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"PLD: fast FPGA compilation to make reconfigurable acceleration compatible ..."

Yuanlong Xiao et al. (2022)

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DOI: 10.1145/3503222.3507740

access: closed

type: Conference or Workshop Paper

metadata version: 2022-12-05

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  dblp key:
  - conf/asplos/XiaoMBHAGMD22
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  - https://dblp.org/rec/conf/asplos/XiaoMBHAGMD22
Yuanlong Xiao, Eric Micallef, Andrew Butt, Matthew Hofmann, Marc Alston, Matthew Goldsmith, Andrew Merczynski-Hait, André DeHon:
PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development. ASPLOS 2022: 933-945

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