"Low power clock buffer planning methodology in F-D placement for large ..."

Yanfeng Wang et al. (2008)

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DOI: 10.1109/ASPDAC.2008.4483977

access: closed

type: Conference or Workshop Paper

metadata version: 2018-01-30

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  - https://dblp.org/rec/conf/aspdac/WangZCHHB08
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian:
Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC 2008: 370-375

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