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"A current-mode, 3 V, 20 MHz, 9-bit equivalent CMOS sample-and-hold circuit."
Yasuhiro Sugimoto, Tetsuya Iida (1997)
- Yasuhiro Sugimoto, Tetsuya Iida:
A current-mode, 3 V, 20 MHz, 9-bit equivalent CMOS sample-and-hold circuit. ASP-DAC 1997: 685-686
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