"Minimizing clock latency range in robust clock tree synthesis."

Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen (2010)

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DOI: 10.1109/ASPDAC.2010.5419849

access: closed

type: Conference or Workshop Paper

metadata version: 2024-08-09

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Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen:
Minimizing clock latency range in robust clock tree synthesis. ASP-DAC 2010: 389-394

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