"A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation ..."

Yunseong Jo et al. (2025)

> Home

Details and statistics

DOI: 10.1145/3658617.3698481

access: closed

type: Conference or Workshop Paper

metadata version: 2025-03-07

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/aspdac/JoKYH25
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/aspdac/JoKYH25
Yunseong Jo, Taeseung Kang, Jeonghyu Yang, Jaeduk Han:
A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology. ASP-DAC 2025: 338-341

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.