"Post-layout transistor sizing for power reduction in cell-based design."

Masanori Hashimoto, Hidetoshi Onodera (2001)

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DOI: 10.1145/370155.370392

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Masanori Hashimoto, Hidetoshi Onodera:
Post-layout transistor sizing for power reduction in cell-based design. ASP-DAC 2001: 359-365

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